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CY7C1011CV33
2-Mbit (128K x 16) Static RAM
Features
Functional Description
The CY7C1011CV33 is a high performance CMOS static RAM organized as 131,072 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected. To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A16). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. For more information, see the "Truth Table" on page 9 for a complete description of Read and Write modes. The input and output pins (IO0 through IO15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Temperature ranges Commercial: 0C to 70C Industrial: -40C to 85C Automotive-A: -40C to 85C Pin and function compatible with CY7C1011BV33 High speed tAA = 10 ns Low active power 360 mW (max) Data Retention at 2.0 Automatic power down when deselected Independent control of upper and lower bits Easy memory expansion with CE and OE features Available in Pb-free and non Pb-free 44-pin TSOP II, 44-pin TQFP and 48-Ball VFBGA packages

Logic Block Diagram
INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8
ROW DECODER
128K x 16 RAM Array
SENSE AMPS
IO0-IO7 IO8-IO15
COLUMN DECODER
BHE WE CE OE BLE
A10 A11
A12
A14
A15
Cypress Semiconductor Corporation Document Number: 38-05232 Rev. *F
*
198 Champion Court
A13
A16
A9
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 04, 2008
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CY7C1011CV33
Pin Configuration
Figure 1. 44-Pin TSOP II [1] Figure 2. 48-Ball FBGA Pinout [1]
A4 A3 A2 A1 A0 CE IO1 IO2 IO3 IO4 VCC VSS IO5 IO6 IO7 IO8 WE A15 A14 A13 A12 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE BHE BLE IO16 IO15 IO14 IO13 VSS VCC IO12 IO11 IO10 IO9 NC A8 A9 A10 A11 NC
1 BLE IO8 IO9 VSS VCC IO14 IO15 NC
2 OE BHE IO10 IO11 IO12 IO13 NC A8
3 A0 A3 A5 NC NC A14 A12 A9
4 A1 A4 A6 A7 NC A15 A13 A10
5 A2 CE IO2 IO3 IO4 IO5 WE A11
6 NC IO0 IO1 VCC VSS IO6 IO7 NC A B C D E F G H
Figure 3. 44-Pin TQFP II
BHE 35 BLE 34 33 32 31 30 29 28 27 26 25 24 23 21 12 13 14 16 17 18 15 19 20 22 A13
A14
A15
A11
A12
A16
A10 38
1 44 43 42 40 39 37 41 36 CE IO 0 IO 1 IO 2 IO3 VCC VSS IO 4 IO 5 IO 6 IO 7 1 2 3 4 5 6 7 8 9 10 11 IO 15 IO 14 IO 13 IO 12 VSS VCC IO11 IO 10 IO 9 IO 8 NC
WE A0
A1
OE A6
A9
NC
A2
A5
A3
Note 1. NC pins are not connected on the die.
Document Number: 38-05232 Rev. *F
A4
A7
A8
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CY7C1011CV33
Selection Guide
Description Maximum Access Time Maximum Operating Current Comm'l Ind'l Auto-A Maximum CMOS Standby Current Comm'l/Ind'l Auto-A -10 10 90 100 100 10 10 10 10 -12 12 85 95 -15 15 80 Unit ns mA mA mA mA mA
Document Number: 38-05232 Rev. *F
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CY7C1011CV33
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage on VCC Relative to GND[2] .....-0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[2] ...................................... -0.5V to VCC+0.5V DC Input Voltage[2] .................................. -0.5V to VCC+0.5V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage............................................ >2001V (MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial Automotive-A Ambient Temperature (TA) 0C to +70C -40C to +85C -40C to +85C VCC 3.3V 10%
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Leakage Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VI < VCC, Output disabled VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC Com'l/Ind'l Auto-A Com'l/Ind'l Auto-A Com'l Ind'l Auto-A ISB1 Automatic CE Power Down Current --TTL Inputs Automatic CE Power Down Current -- CMOS Inputs Max VCC, CE > VIH Com'l/Ind'l VIN > VIH or VIN < VIL, f = fMAX Auto-A Max VCC, CE > VCC - 0.3V, Com'l/Ind'l VIN > VCC - 0.3V, or Auto-A VIN < 0.3V, f = 0 Test Conditions VCC = Min, IOH = -4.0 mA VCC = Min, IOL = 8.0 mA 2.0 -0.3 -1 -1 -1 -1 -10 Min 2.4 0.4 VCC + 0.3 0.8 +1 +1 +1 +1 90 100 100 40 40 10 10 10 10 mA 40 40 mA 85 95 80 mA -1 +1 -1 +1 A 2.0 -0.3 -1 Max 2.4 0.4 VCC + 0.3 0.8 +1 2.0 -0.3 -1 -12 Min Max 2.4 0.4 VCC + 0.3 0.8 +1 -15 Min Max Unit V V V V A
ISB2
Note 2. VIL (min) = -2.0V for pulse durations of less than 20 ns.
Document Number: 38-05232 Rev. *F
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CY7C1011CV33
Capacitance
Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max 8 8 Unit pF pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters. Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board TSOP II 44.56 10.75 TQFP 42.66 14.64 FBGA 46.98 9.63 Unit C/W C/W
JA JC
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms [3]
10-ns devices: OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V 12-, 15-ns devices: Z = 50 3.3V
R 317
30 pF*
OUTPUT
30 pF*
R2 351
(a)
(b)
High-Z characteristics: R 317 3.0V GND ALL INPUT PULSES 90% 10% 90% 10% 3.3V OUTPUT 5 pF R2 351
Rise Time: 1 V/ns
(c)
Fall Time: 1 V/ns
(d)
Note 3. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure 4 (a). All other speeds are tested using the Thevenin load shown in Figure 4 (b). High-Z characteristics are tested for all speeds using the test load shown in Figure 4 (d).
Document Number: 38-05232 Rev. *F
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CY7C1011CV33
Switching Characteristics
Over the Operating Range [4] Parameter Read Cycle tpower[5] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW VCC(Typical) to the First Access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High CE HIGH to High
[6]
Description
-10 Min 1 10 10 3 10 5 0 5 3 5 0 10 5 0 5 10 7 7 0 0 7 5 0 3 5 7 8 12 8 8 0 0 8 6 0 3 0 0 3 0 3 Max Min 1 12
-12 Max Min 1 15 12 3 12 6 0 6 3 6 0 12 6 0 6 15 10 10 0 0 10 7 0 3 6 10
-15 Max
Unit
s ns 15 15 7 7 7 15 7 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 ns ns
Z[6, 7] Z[6, 7]
CE LOW to Low Z[6] CE LOW to Power Up CE HIGH to Power Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z
[8, 9]
Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low Z[6] WE LOW to High Z[6, 7] Byte Enable to End of Write
Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. 5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 6. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of "AC Test Loads and Waveforms" on page 5. Transition is measured 500 mV from steady state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write. The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 38-05232 Rev. *F
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CY7C1011CV33
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled)[10, 11]
tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Figure 6. Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS tRC CE tACE OE tDOE BHE, BLE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% tHZCE tHZBE DATA VALID tPD 50% ICC ISB tHZOE
HIGH IMPEDANCE
Notes 10. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05232 Rev. *F
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CY7C1011CV33
Switching Waveforms
(continued) Figure 7. Write Cycle No. 1 (CE Controlled)[13, 14]
tWC ADDRESS
tSA CE tAW
tSCE
tHA tPWE
WE tBW BHE, BLE tSD DATA IO tHD
Figure 8. Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS
tSA BHE, BLE
tBW
tAW tPWE WE tSCE CE tSD DATA IO tHD
tHA
Notes 13. Data IO is high impedance if OE, BHE, and/or BLE = VIH. 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05232 Rev. *F
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CY7C1011CV33
Switching Waveforms
(continued) Figure 9. Write Cycle No. 3 (WE Controlled, LOW)
tWC ADDRESS
tSCE CE tAW tSA WE tBW BHE, BLE tPWE
tHA
tHZWE DATA IO
tSD
tHD
tLZWE
Truth Table
CE H L L L L L L L OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X IO0- IO7 IO8 - IO15 High Z Data Out Data Out High Z Data In Data In High Z High Z High Z Data Out High Z Data Out Data In High Z Data In High Z Mode Power Down Read - All Bits Read - Lower Bits Only Read - Upper Bits Only Write - All Bits Write - Lower Bits Only Write - Upper Bits Only Selected, Outputs Disabled Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Power Standby (ISB)
Document Number: 38-05232 Rev. *F
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CY7C1011CV33
Ordering Information
Speed (ns) 10 Ordering Code CY7C1011CV33-10ZC CY7C1011CV33-10ZXC CY7C1011CV33-10ZXI CY7C1011CV33-10BVI CY7C1011CV33-10ZSXA 12 CY7C1011CV33-12ZC CY7C1011CV33-12ZXC CY7C1011CV33-12ZI CY7C1011CV33-12ZXI CY7C1011CV33-12AXI CY7C1011CV33-12BVI 15 CY7C1011CV33-15ZXC Package Diagram 51-85087 44-pin TSOP II 44-pin TSOP II (Pb-Free) 51-85087 44-pin TSOP II (Pb-Free) 51-85150 48-ball (6 x 8 x 1 mm) VFBGA 51-85087 44-pin TSOP II (Pb-Free) 51-85087 44-pin TSOP II 44-pin TSOP II (Pb-Free) 51-85087 44-pin TSOP II 44-pin TSOP II (Pb-Free) 51-85064 44-pin TQFP (Pb-Free) 51-85150 48-ball (6 x 8 x 1 mm) VFBGA 51-85087 44-pin TSOP II (Pb-Free) Commercial Industrial Automotive-A Commercial Industrial Package Type Operating Range Commercial
The 44 pin TSOP II package containing the Automotive grade device is designated as "ZS", while the same package containing the Commercial/Industrial grade device is "Z".
Document Number: 38-05232 Rev. *F
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CY7C1011CV33
Package Diagrams
Figure 10. 44-Pin Thin Small Outline Package Type II
51-85087-*A
Document Number: 38-05232 Rev. *F
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CY7C1011CV33
Package Diagrams
(continued) Figure 11. 44-pin Thin Plastic Quad Flat Pack
12.000.25 SQ 10.000.10 SQ
44 34
0 MIN.
1 33
0.370.05 STAND-OFF 0.05 MIN. 0.15 MAX.
R. 0.08 MIN. 0.20 MAX. 0.25 GAUGE PLANE
R. 0.08 MIN. 0.20 MIN. 0.20 MIN.
0-7 0.600.15
1.00 REF.
11 23
0.80 B.S.C. DETAIL
A
12
22
NOTE: 1. JEDEC STD REF MS-026
SEATING PLANE 1.60 MAX. 121 (8X)
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS
1.400.05 0.10 0.20 MAX.
SEE DETAIL
A
51-85064-*C
Document Number: 38-05232 Rev. *F
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CY7C1011CV33
Package Diagrams
(continued) Figure 12. 48-Ball FBGA (6 x 8 x 1 mm)
TOP VIEW
BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B
A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C 8.000.10 8.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75 B 6.000.10
0.55 MAX.
0.25 C
0.15(4X) 0.210.05 0.10 C
SEATING PLANE 0.26 MAX. C 1.00 MAX
51-85150-*D
Document Number: 38-05232 Rev. *F
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CY7C1011CV33
Document History Page
Document Title: CY7C1011CV33, 2-Mbit (128K x 16) Static RAM Document Number: 38-05232 REV. ** *A *B ECN NO. 117132 118057 119702 Issue Date 07/31/02 08/19/02 10/11/02 Orig. of Change HGK HGK DFP New Data Sheet Pin configuration for 48-ball FBGA correction Updated FBGA to VFBGA; updated package code on page 8 to BV48A. Updated address pinouts on page 1 to A0 to A16. Updated CMOS standby current on page 1 from 8 to 10 mA Added lead-free parts in Ordering Information Table Corrected typo in the Logic Block Diagram on page# 1 Included the Maximum Ratings for Static Discharge Voltage and Latch up Current on page# 3 Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Updated the Ordering Information Table Added Thermal Resistance Table Description of Change
*C *D
386106 498501
See ECN See ECN
PCI NXR
*E *F
522620
See ECN
VKN
1891366 See ECN VKN/AESA Added -10ZSXA part Updated Ordering Information table
(c) Cypress Semiconductor Corporation, 2002-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05232 Rev. *F
Revised January 04, 2008
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